The present disclosure relates to a dynamic multiple-field history buffer that preserves register content from different register types.
Modern information handling systems typically implement out-of-order microprocessor designs that store register contents at “checkpoints” so the microprocessor can revert back to a register state prior to an interruption if required, such as during a branch instruction. When a processor reaches branch instruction, the processor selects a most likely path and begins to process instructions down the selected path. The processor, however, stores register contents at the branch in case the selected path is the incorrect path and the processor needs to revert back to the register state prior to the mis-predicted path.
Processors may store the register contents at checkpoints in history buffers. Traditional history buffers allow a processor to store the entire contents of a particular register in a history buffer entry, such as storing the entire contents of a general purpose register (GPR) into a single history buffer entry. Each history buffer entry includes a single instruction tag (itag) field that stores an itag value from the GPR, which the processor utilizes to determine which history buffer content should be restored into specific registers if required.
Processors may use several register “types” to store contents, such as general purpose registers, exception and status registers (FPSCR, XER, and CR). The different register types may utilize different data field widths depending upon the data length of what is stored in the registers. As such, traditional architectures utilize a different history buffer for each register type whereby the different history buffers include history buffer entries with data widths matching the different register type data entries.